1. Field of the Invention:
The present invention relates generally to a process for etching dielectric layers in the fabrication of semiconductor devices. More particularly, it relates to such a process for etching oxides. Most especially, it relates to such a process for contact etching, particularly in high aspect ratio geometries.
2. Description of the Prior Art:
Reactive ion etch (RIE) processes for etching oxide layers are well known in the art and have achieved wide acceptance in the semiconductor industry. For example, apparatus for carrying out such processes is described in commonly assigned U.S. Pat. No. 4,842,683, issued Jun. 27, 1989 to Cheng et al. and U.S. Pat. No. 4,668,338, issued May 26, 1987 to Maydan et al. Apparatus for carrying out such processes is commercially available from Applied Materials, Santa Clara, Calif., under the designation Precision 5000E and 8300. Currently, gas mixtures used for etching oxide in the Precision 5000E apparatus include mixtures of CHF.sub.3 and O.sub.2 ; CHF.sub.3, Ar and O.sub.2 ; CHF.sub.3, Ar and CF.sub.4 ; CHF.sub.3, He, and CF.sub.4 and CHF.sub.3, Ar and C.sub.2 F.sub.6. These chemistries can achieve high etch rates and high selectivities, but oxide to polysilicon selectivities of greater than 25:1 cannot be achieved without an increase in the RIE lag to greater than 15 percent. The term "RIE lag" refers to the percentage difference in the oxide etch depth of 1 micron (.mu.) wide contacts compared with the oxide etch depth of 0.5 .mu. wide contacts under the same process conditions.
In detailed studies of the standard oxide etch chemistry of CHF.sub.3, Ar and CF.sub.4 and standard 5000E apparatus for a high aspect ratio contact etch, it was determined that there would be difficulty meeting the following specification:
______________________________________ RIE Lag &lt;10% in 0.5 .mu.m contacts compared with 1.0 .mu.m contacts at 2.0 .mu.m depth. Etch Rate &gt;4000 .ANG./min, undoped oxide Uniformity &lt;10% 3.sigma., 6 mm edge exclusion Selectivity &gt;30:1 to doped polysilicon Profile &gt;85 degrees. ______________________________________
It was found that there is always a compromise between lag and selectivity. The etch rate, uniformity and profile specifications can be achieved over a large process window, but it is hard to achieve a selectivity greater than 20:1 with a lag of less than 10%. This is also true for cathode temperatures as low as -40.degree. C. At such lower cathode temperatures, the process window is reduced further because the profile angle is worse due to increased polymer deposition.